Soft Error Reduction of Logical Circuits by Using RAR Methodology

Due to shrinking feature sizes and decreasing supply voltages in current technology scaling trends, the reliability of circuit would be affected by radiation induced particle hits. Nowadays soft errors are main factor in reliability degradation of logic circuits, which have been a great concern in memories also. Here, we present a systematic and integrated methodology for circuit robustness to soft errors. Based on redundancy addition and removal (RAR) method, our proposed work explains that the soft error rate (SER) reduction framework provides eliminating those gates by means of large support to the complete SER. The plan called resizing is included into our framework, as post-RAR additive SER optimization. We can minimize area and power overheads by identifying most critical gates to be upsized while continuing a high level of soft error toughness.